Design and Verification of Asynchronous FIFO
The major issue in transferring a data from one clock domain to another clock domain is synchronization and data loss which affects the performance and data transfer speed. To overcome this, asynchronous FIFOs are implemented using gray codes and dual flip-flop synchronizers. In this proposed technique, it consumes low power and ensures safe transmission of data. Transistor count, power dissipation and delay are minimized and speed is increased. RTL Verilog coding is used. It is observed that the power will be reduced to half of its value. By using the Asynchronous FIFO designed using gray pointer and dual flip-flop we can transmit the data safely with no data loss and we can further reduce the power, area and delay. Performance, efficiency and speed also gets increased. This can be implemented using Verilog coding and simulated in Xilinx tool. It verified in real time using Spartan-6 FPGA kit.